An histogram based procedure for current testing of active defects

The purpose of this paper is to propose a new histogram-based diflerential current testing procedure of active defects. This procedure contains three steps: Preanalysis, Failure Analysis, and Production Testing. The main objehtives of the Pre-analysis are to provide information on the most frequent active current defects and to help ‘setting the limits between faulty and fault-free devices: these limits are then investigated during the Failure Analysis step in’order to set the threshold between faulty and fault-free ICs. During the Production Testing step, this thtieshold is compared to the highest peak value appearing in a histogram built for each tested IC. Some selected results are presented, which confirm the test quality gain increase by using diflerential IDDQ instead of IDDQ itself as well as the additional reduction of bad test decision that, can be obtained by a wise selection of test vectors reducing the vector-to-vector current variations.